1. Field of the Invention
The present invention relates to an integrated circuit and method for testing memory on the integrated circuit.
2. Description of the Prior Art
It is becoming more and more common for integrated circuits to include embedded memory to allow rapid access to data by processing logic provided on the integrated circuit. As the use of embedded memory continues to increase, thorough testing and defect diagnosis has become a key requirement to ensure product quality and enhance product yield. Whilst embedded memory presents significant system performance and cost reduction advantages, it brings its own testing issues. Test vector style tests are not suitable for verifying embedded memory arrays for a number of reasons. Firstly, the time spent in the manufacturing test grows exponentially as the embedded memory die area increases, which often makes such test vector style testing too costly. Furthermore, it is sometimes not possible to create a set of vectors that can detect all possible types of memory defect.
A known technique which alleviates such problems is to provide the integrated circuit with a memory Built In Self-Test (BIST) controller. In simplistic terms, a memory BIST controller is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the embedded memory. These tests can be executed at the design's full operating frequency to prove the memory operations and identify errors caused by silicon defects.
Typically, known memory BIST controller designs only allow the test algorithms to be programmed when the RTL (Register Transfer Language) for the integrated circuit is generated, and these test algorithms can then not be changed thereafter. However, such an approach has the disadvantage that the algorithms programmed at the RTL stage may later turn out not to include a needed algorithm, thereby requiring redesign, or may indeed include an algorithm that isn't actually required, thereby wasting test time. Accordingly, there is a need to provide more flexibility in algorithm selection, particularly in situations where the memory BIST controller is being designed without a knowledge of the final memory that will be placed within the integrated circuit.
To seek to provide such flexibility, ARM Limited of Cambridge, United Kingdom have developed a memory BIST controller that enables a test algorithm to be programmed after the integrated circuit has been produced in silicon. In particular, an interface is provided through which the desired test algorithm can be entered. However, such an approach requires a separate instruction load procedure to be performed for each test algorithm that is to be run by the memory BIST controller for the embedded memory devices. Since the interface will not typically be able to operate at the full operating speed of the integrated circuit, it is typically necessary to switch to a slower clock, execute a load instruction in order to load through the interface the required test algorithm, and then switch back to a fast clock, whereafter the memory BIST controller can execute the test algorithm in order to perform the test at the full operating frequency of the integrated circuit.
Whilst such an approach does provide some flexibility with regard to programming of test algorithms, it has been found that such an approach can significantly add to the time required to perform testing of the embedded memory, and also increases the complexity of the test procedure. In particular, such a load procedure needs to be performed for each different test algorithm to be programmed into the memory BIST controller after the integrated circuit silicon has been produced, and typically for each embedded memory that is to be subjected to execution of that test algorithm. Whilst it is possible to provide an interface large enough to enable multiple embedded memories to be tested in parallel this increases the complexity and expense of the BIST controller, and even then it is still necessary to perform the load procedure for each different test algorithm to be programmed into the memory BIST controller.
Accordingly, it would be desirable to provide an improved technique for allowing test algorithms to be programmed at run time, and in particular to develop a technique which reduced the time required for such testing and the complexity of the test process whilst retaining such flexibility.